bitborn/ CPU LAB

THE MACHINE ROOM / 16-BIT TEACHING MODEL

See every
state change.

One instruction. A handful of bits.
A machine that makes sense.

Step through literal binary and trace the path from instruction bytes to registers, flags, stack and memory.

EDUCATIONAL SIMULATION · NOT NATIVE CPU EXECUTION
READY0000 / 4096 steps

Loading the lab…

Binary Time Machine · 0 / 0 recorded. Back/Forward restore exact recorded registers, flags, RAM and output. Step after rewinding replaces the future. Keys: B / F. Reset or loading a program clears history.

Recorded execution timeline

RESTORE / INSPECT

    Select any recorded state. Arrow keys move one state; Home/End select the first/last. Highlighted changes compare the state you left with the one you selected. Restoring states never executes new instructions.

    Register file

    16 BITS / EACH

    FLAGS

    1 set · 0 clear · ? undefined

    1 Underlined bits changed since the previously displayed state. Bits are numbered 15 → 0.

    Instruction path

    0 BYTES

    · Signed comparison exercise (.bits) ↓ · Carry and borrow exercise (.bits) ↓ · Self-modifying instruction (.bits) ↓

    BREAKCS:IPDECODED BYTES

    Click a circle to pause before an instruction. Step executes it; Run resumes from it.

    Follow the instruction pointer

    0000:7C00
    PREVIOUS / EXECUTED—No instruction executed
    CURRENT / TO EXECUTE——
    NEXT / SEQUENTIAL—Branch outcome may differ

    IP starts at 7C00.

    Step to see exactly which register bits, flags and memory bytes change.

    Stack

    GROWS ↓ IN ADDRESS
    SS:SP 0000:7C00Initial stack pointer

    Eight words beginning at SS:SP. Each word is stored low byte first; the arrow marks the current top.

    Memory microscope

    1 MiB MODELED
    —

    Enter 00000–FFFFF. Up to 64 bytes; underlined bytes changed since the previously displayed state.

    Literal binary program

    NO ASSEMBLER

    Up to 512 bytes. Source uses eight literal 0s or 1s per byte; whitespace and # comments are allowed. .bin files import raw bytes. Loading resets state and clears breakpoints; invalid input keeps the current program.

    Two ASCII hex digits per byte, e.g. B8 2A 00. Valid binary drafts update this hex view without loading. Load hex replaces the binary draft, omits its comments and resets the model. No instruction is generated from a name.

    Exports preserve loaded bytes before self-modification, omitting comments/pending drafts. Raw programs have no BIOS framing or ELF headers.

    Open shared program →

    1–512 loaded bytes, before self-modification. Comments, pending drafts, registers and history are omitted. The link contains the bytes in its URL fragment and opens paused; anyone with the link can read them.

    Modeled output

    INT 10h / COM1

    Screen teletype

    ∅

    Serial

    ∅

    Output is recorded in this page. Simulated instructions cannot access your files or the network.

    What this model represents

    This is a bounded educational 16-bit simulation of selected x86 encodings, not a complete emulator or native CPU. It starts from a deterministic state: general and segment registers and flags are zero, IP is 7C00, SP is 7C00. This is not a BIOS register snapshot. Bit 1 of FLAGS is fixed to 1; undefined AF is shown as ? and encoded as 0 in the displayed word.

    The model has 1 MiB of memory and a 4,096-step budget per reset. Physical addresses use ((segment << 4) + offset) & FFFFF: A20 is masked. Register offsets wrap to 16 bits; word accesses beginning at offset FFFF stop because crossing a segment limit is outside this subset. There is no interrupt delivery, BIOS implementation, timing model or device emulation; only explicitly supported teletype and serial behavior. Unsupported instructions stop with an explanation. The listing decodes sequentially; a branch can skip bytes or land at a different boundary.

    Keyboard: S steps; Space runs or pauses; R resets. Shortcuts are inactive while editing a form field. Every control also works with Tab and Enter.